Optical lithography technologies for 45-nm node CMOS

Shoji Mimotogi; Fumikatsu Uesawa; Suigen Kyoh; Hiroharu Fujise; Eishi Shiobara; Mikio Katsumata; Hiroki Hane; Tomohiro Sugiyama; Koutaro Sho; Maki Miyazaki; Kazuhiro Takahata; Hideki Kanai; Kazuya Sato; Kohji Hashimoto

doi:10.1117/12.600948

12 May 2005 Optical lithography technologies for 45-nm node CMOS

Shoji Mimotogi, Fumikatsu Uesawa, Suigen Kyoh, Hiroharu Fujise, Eishi Shiobara, Mikio Katsumata, Hiroki Hane, Tomohiro Sugiyama, Koutaro Sho, Maki Miyazaki, Kazuhiro Takahata, Hideki Kanai, Kazuya Sato, Kohji Hashimoto

Author Affiliations +

Proceedings Volume 5754, Optical Microlithography XVIII; (2005) https://doi.org/10.1117/12.600948
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are proposed. The alternating phase shift mask has been applied to obtain high accurate CD controllability for gate level. Since the sensitivity to lens aberration is high, design rule is restricted. Immersion lithography with hyper NA over 1.0 is necessary for contact hole level to get large DOF margin. Since the mask enhanced error factor is large, high accurate CD uniformity on mask is necessary. Using hyper NA immersion tool, high density SRAM whose area is 0.25um2 can be clearly resolved.

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Shoji Mimotogi, Fumikatsu Uesawa, Suigen Kyoh, Hiroharu Fujise, Eishi Shiobara, Mikio Katsumata, Hiroki Hane, Tomohiro Sugiyama, Koutaro Sho, Maki Miyazaki, Kazuhiro Takahata, Hideki Kanai, Kazuya Sato, and Kohji Hashimoto "Optical lithography technologies for 45-nm node CMOS", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); https://doi.org/10.1117/12.600948

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