H.264/AVC is the most recent and promising international video coding standard developed by the ITU-T Video Coding Experts Group in conjunction with the ISO/IEC Moving Picture Experts Group. This standard has been designed in order to provide improved coding efficiency and network adaptation. In this sense, H.264/AVC provides superior features when compared with its ancestors such as MPEG-2, MPEG-4 and H.263 but at the expenses of a prohibitive computational cost for real time applications. In particular, the motion estimation results to be the most intensive task in the whole encoding process, and for this reason, efficient architectures as the one presented in this paper to compute the 41 motion vectors per macroblock required by the H.264/AVC video coding standard, are needed in order to meet real conditions. This paper deals with a low cost VLSI architecture capable to obtain half and quarter pixel precision motion vectors, applying the correspondent techniques in order to obtain these motion vectors as demanded by the H.264/AVC standard. Techniques such as the reuse of the results obtained for smaller blocks and the possibility of avoiding the use of certain motion estimation modes have been introduced in order to obtain a flexible low-power hardware solution. As a result, the proposed architecture has been synthesized and generated to a commercial FPGA device, producing a fully functional embedded prototype capable of processing up to QCIF images at 30 fps with low area occupation.