Translator Disclaimer
Paper
30 June 2005 Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters
Author Affiliations +
Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608352
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain
Abstract
The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
V. Ferragina, A. Frassone, N. Ghittori, P. Malcovati, and A. Vigna "Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608352
PROCEEDINGS
8 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

The Square Root In Signal Processing
Proceedings of SPIE (December 06 1989)
Statistical design of stack filters
Proceedings of SPIE (September 24 1998)
VLSI processor for high-performance arithmetic computations
Proceedings of SPIE (December 01 1991)

Back to Top