Paper
30 June 2005 Performance analysis of full adders in CMOS technologies
Javier Castro, Pilar Parra, Antonio J. Acosta
Author Affiliations +
Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608269
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain
Abstract
Full adders are one of the most important building blocks in VLSI digital arithmetic. The area, electrical, timing, power consumed and noise generated characteristics of this cell are strongly dependent on the design technique. An exhaustive work taking into account the above parameters is done, and that complete analysis will be of utility for the community of digital designers. Emphasis will be done in power/noise figures, of most important concern in current CMOS mixed-signal design. The full adders considered are those using complementary CMOS, pass-transistor logic, double pass-transistor logic, and two versions based on CMOS transmission gate. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 μm CMOS technology. The main results obtained are, on one hand, the selection of a logic family for a specific application and, on the other hand, the selection of a specific full adder structure for an optimized parameter option -power, noise or speed.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Javier Castro, Pilar Parra, and Antonio J. Acosta "Performance analysis of full adders in CMOS technologies", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608269
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KEYWORDS
Logic

Transistors

CMOS technology

Very large scale integration

Picosecond phenomena

Power supplies

Plasma display panels

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