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28 June 2005 An extension method of metal layer layout in mask data preparation for robust processes
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Proceedings Volume 5853, Photomask and Next-Generation Lithography Mask Technology XII; (2005) https://doi.org/10.1117/12.617135
Event: Photomask and Next Generation Lithography Mask Technology XII, 2005, Yokohama, Japan
Abstract
Application of DFM (Design for Manufacturability) techniques to the design of random logic metal-layers with million nodes is indispensable for manufacturing semiconductor devices with the node of 90 nm and the bellow. Critical dimension lines corresponding to minimum design rules do not have sufficient process margin due to the presence of focus variation of ArF scanner. This often induces resist-line narrowing, which causes circuit-speed degradations and Cu opens, finally leading to serious yield losses. There are numerous studies on techniques to expand the process margin, such as the placement of dummy and assist patterns. However such techniques can not sometimes be applied due to restrictions of design rule. We note that the presence of such augmented patterns increases the wire capacitance and mask TAT (turn around time). We have developed an automatic layout-pattern generation method which extends the line-end of patterns adjacent to isolated patterns. This resulted in a significant improvement of the process margin of isolated patterns.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kensuke Tsuchiya, Kazuhisa Ogawa, Satomi Nakamura, Kazuyoshi Kawahara, Hidetoshi Oishi, and Hidetoshi Ohnuma "An extension method of metal layer layout in mask data preparation for robust processes", Proc. SPIE 5853, Photomask and Next-Generation Lithography Mask Technology XII, (28 June 2005); https://doi.org/10.1117/12.617135
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