Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

Michael Kelly; Robert Berger; Curtis Colonero; Mark Gregg; Joshua Model; Daniel Mooney; Eric Ringdahl

doi:10.1117/12.619284

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25 August 2005 Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

Michael Kelly, Robert Berger, Curtis Colonero, Mark Gregg, Joshua Model, Daniel Mooney, Eric Ringdahl

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Proceedings Volume 5902, Focal Plane Arrays for Space Telescopes II; 59020J (2005) https://doi.org/10.1117/12.619284
Event: Optics and Photonics 2005, 2005, San Diego, California, United States

Abstract

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18-micron CMOS process, and was designed to operate with Hg_xCd_1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.

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Michael Kelly, Robert Berger, Curtis Colonero, Mark Gregg, Joshua Model, Daniel Mooney, and Eric Ringdahl "Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays", Proc. SPIE 5902, Focal Plane Arrays for Space Telescopes II, 59020J (25 August 2005); https://doi.org/10.1117/12.619284

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