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5 November 2005 Full-chip poly gate critical dimension control using model based lithography verification
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Abstract
Gate CD (Critical Dimension) control is an important factor in determining semiconductor manufacturing yield. Therefore, its verification prior to mask tape-out is essential to save development time and cost. Not only is fatal-error detection required to ensure high yield, tight CD control in the gate region is equally critical in sub-micron IC manufacturing. As fast turn around time is achieved for very large data through scalable distributed processing, model-based lithography verification has been utilized for checking the post mask synthesis data quality before mask tape out and RET/OPC process development. In this paper, we introduce a comprehensive methodology to study and qualify Poly mask layer using a model based lithography verification tool. This flow will include CD checks on both gate-width and gate- length dimensions. Gate CD distribution plots on the poly layer will be done across a complete range of target CDs in order to investigate wafer CD uniformity errors on full-chip level under various process conditions. In addition, the traditional edge-placement detection will be discussed and compared to absolute CD verification process.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daniel N. Zhang, Juhwan Kim, Lantian Wang, and Zongwu Tang "Full-chip poly gate critical dimension control using model based lithography verification", Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 59925E (5 November 2005); https://doi.org/10.1117/12.632302
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