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24 October 2005 Photonic crystal fabrication on silicon-on-insulator (SOI) using 248nm and 193nm lithography
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We report Photonic Crystal (PhC) designs fabricated in silicon-on-insulator wafers (SOI) using 248 nm & 193 nm DUV lithography. Emphasis was on demonstrating unique PhC effects through the use of standard CMOS equpiment and process development of an optical test chip using a high-volume manufacturing facility. Most of the planar 2-D PhCs waveguides were designed using a triangular lattice of holes. An extensive range of test structures were also designed, including W1 and W3 waveguides in both triangular and square lattices. The use of optical proximity correction (OPC) and variations of pitch and hole dimensions allowed for a large design-of-experiment not practical using the more conventional e-beam direct-write approach. Smart Cut SOI wafers with a thin epitaxial Si layer on a 2μm buried SiO2 layer were first processed and characterized using 248 nm lithography. Preliminary pitch/hole patterning requirements were 400nm/200nm. Resist was changed from high- to low-contrast resist to compensate for the high sensitivity of critical hole dimension to exposure dose. Optical characterization data of PhC test structures were used to map band structure calculations and more accurately determine the PhC effective index; results were used to model more accurate pitch/hole values. Successful processing results were also obtained using 193nm lithography to resolve PhC pitch/hole dimensions of ~280/180nm. Optical characterization data are being used to refine next-generation PhC designs.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Salib, Albert Michaeli, Adi Lazar, Haviv Bechor, Michael Settle, and Thomas F. Krauss "Photonic crystal fabrication on silicon-on-insulator (SOI) using 248nm and 193nm lithography", Proc. SPIE 6017, Nanophotonics for Communication: Materials and Devices II, 60170B (24 October 2005);

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