Parallel implementation of Mpeg-2 video decoder

Abhik Sarkar; Kaushik Saha; Srijib Maiti

doi:10.1117/12.642245

15 January 2006 Parallel implementation of Mpeg-2 video decoder

Abhik Sarkar, Kaushik Saha, Srijib Maiti

Proceedings Volume 6074, Multimedia on Mobile Devices II; 60740A (2006) https://doi.org/10.1117/12.642245
Event: Electronic Imaging 2006, 2006, San Jose, California, United States

Abstract

The demand for real-time MPEG decoding is growing in multimedia applications. This paper discusses a hardware-software co-design for MPEG-2 Video decoding and describes an efficient parallel implementation of the software module. We have advocated the usage of hardware for VLD since it is inherently serial and efficient hardware implementations are available. The software module is a macro-block level parallel implementation of the IDCT and Motion Compensation. The parallel implementation has been achieved by dividing the picture, into two halves for 2-processor implementation and into four quadrants for 4-processor implementation, and assigning the macro-blocks present in each partition to a processor. The processors perform IDCT and Motion Compensation in parallel for the macro-blocks present in their allotted sections. Thus each processor displays 1/no_of_processors of a picture frame. This implementation minimizes the data dependency among processors while performing the Motion Compensation since data dependencies occur only at the edges of the divided sections. Load balancing among the processors has also been achieved, as all the processors perform computation on an equal number of macro-blocks. Apart from these, the major advantage is that the time taken to perform the IDCT and Motion Compensation reduces linearly with an increase in number of processors.

Citation Download Citation

Abhik Sarkar, Kaushik Saha, and Srijib Maiti "Parallel implementation of Mpeg-2 video decoder", Proc. SPIE 6074, Multimedia on Mobile Devices II, 60740A (15 January 2006); https://doi.org/10.1117/12.642245

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