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28 February 2006 Lithography-grade tungsten-copper substrates for wafer level packaging
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Abstract
Wafer-level packaging can result in significant yield improvement, cost savings, and other improvements in function. For power devices, mismatch between coefficients of thermal expansion (CTE's) between the device and the mounting substrate or package can induce stress that reduces reliability. Adapting CTE-matched composite materials to wafer-level packaging schemes would be beneficial. We describe processes and show data for tungsten-copper substrates that meet wafer specifications for form and finish.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bob Cronk and Greg Rudd "Lithography-grade tungsten-copper substrates for wafer level packaging", Proc. SPIE 6126, Photonics Packaging and Integration VI, 612608 (28 February 2006); https://doi.org/10.1117/12.646914
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