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24 March 2006 Toward full-chip prediction of yield-limiting contact patterning failure: correlation of simulated image parameters to advanced contact metrology metrics
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Electrical failure due to incomplete contacts or vias has arisen as one of the primary modes of yield loss for 130 nm and below designs in manufacturing. Such failures are generally understood to arise from both random and systematic sources. The addition of redundant vias, where possible, has long been an accepted DFM practice for mitigating the impact of random defects. Incomplete vias are often characterized by having a diameter near the target dimension but a depth of less than 100% of target. As such, it is a difficult problem to diagnose and debug in-line, since bright and dark field optical inspection systems cannot typically distinguish between a closed, partially open and fully open contact. Advanced metrology systems have emerged in recent years to meet this challenge, but no perfect manufacturing solution has yet been identified for full field verification of all contacts. Voltage Contrast (VC) SEM metrology biases the wafer to directly measure electrical conductivity after fill / polish, and can therefore easily discern a lack of electrical connection to the underlying conductor caused by incomplete photo, etch, or fill processing. While an entire wafer can in principal be VC scanned, throughput limitations dictate very sparse sampling in manufacturing. SEM profile grading (PG) leverages the rich content of the secondary electron waveform to decipher information about the bottom of the contact. Several authors have demonstrated an excellent response of the Profile Grade to intentional defocus vectors. However, the SEM can only target discreet or single digit groupings of contacts, and therefore requires intelligent guidance to identify those contacts which are most prone to failure, enabling protection of the fab WIP. An a-priori knowledge of which specific contacts in a layout are most likely to fail would prove very useful for proactive inspection in manufacturing. Model based pre-manufacturing verification allows for such knowledge to be communicated to manufacturing. This paper will focus on 130 nm node contact patterning, and will correlate SEM Profile Grade output to the extensive suite of model-based image tags from the CalibreTM opc-verification engine. With an understanding of which image parameters are most highly correlated to the occurrence of incomplete contact formation for a given process, the process model can be used to automatically direct inspection metrology to those layout instances that pose the highest risk of patterning failure through the lithographic process window. Such an approach maximizes the value content of in-line metrology.
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John L. Sturtevant and Dyiann Chou "Toward full-chip prediction of yield-limiting contact patterning failure: correlation of simulated image parameters to advanced contact metrology metrics", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 615209 (24 March 2006);

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