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24 March 2006 Integrated scatterometry in high-volume manufacturing for polysilicon gate etch control
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For several years, integrated scatterometry has held the promise of wafer-level process control. While integrated scatterometry on lithography systems is being used in manufacturing, production implementation on etch systems is just beginning to occur. Because gate patterning is so important to yield, gate linewidth control is viewed by many as the most critical application for integrated scatterometry on etch systems. IBM has implemented integrated scatterometry on its polysilicon gate etch systems to control gate linewidth for its 90 nm node SOI-based microprocessors in its 300 mm manufacturing facility. This paper shows the performance of the scatterometry system and the equipment-based APC system used to control the etch process. Some of the APC methodology is described, as well as sampling strategies, throughput considerations, and scatterometry models. Results reveal that the scatterometry measurements correlate well to CD-SEM measurements before and after etch, and also correlate to electrical measurements. Finally, the improvement in linewidth distribution following the implementation of feedforward and feedback control in full manufacturing is shown.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Matthew Sendelbach, Andres Munoz, Kenneth A. Bandy, Dan Prager, and Merritt Funk "Integrated scatterometry in high-volume manufacturing for polysilicon gate etch control", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61520F (24 March 2006);

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