The goal of overall process and yield improvement requires a litho defect management and reduction strategy, which includes several layers of tactical methods. Defects may be identified through a number of schemes, including After-Develop Inspection (ADI), which was the primary tool in this study in our 0,13μ fab. Defects on 193nm contact hole lithography were identified using a KLA-Tencor 2351 High Resolution Imaging Patterned Wafer Inspection System, coupled with in-line Automatic Defect Classification (iADC). The optimized inspection was used at the core of the Photo Cell Monitor (PCM) to isolate critical defect types. PCM uses the fab's standard production resist coat, exposure, develop, and rinse process, with the focus and exposure optimized for resist on silicon test wafers. Through Pareto analysis of 193nm defects, one defect type, called satellite spot, was targeted for immediate improvement and monitoring. This paper describes the work done in improving the litho defectivity. The work includes optimization of inspection and classification parameters and the Design of Experiments (DOE) to identify the source (including the interaction between the resist and developer) and contributing factors. Several process modifications were identified which resulted in lowered defectivity up to complete suppression of satellite spot defects, although at higher process complexity and cost. This work was also done in conjunction with resist suppliers, which used the same inspection to confirm the problem at their facilities. The work with the suppliers continues with the goal of identifying a less expensive permanent solution.