Self-aligned direct write of a double-sided transistor gate on membrane using an evaporated e-beam resist

Jacques Beauvais; Prasad Kelkar; Eric Lavallée; Dominique Drouin; Kien Mun Lau

doi:10.1117/12.656823

29 March 2006 Self-aligned direct write of a double-sided transistor gate on membrane using an evaporated e-beam resist

Jacques Beauvais, Prasad Kelkar, Eric Lavallée, Dominique Drouin, Kien Mun Lau

Proceedings Volume 6153, Advances in Resist Technology and Processing XXIII; 615348 (2006) https://doi.org/10.1117/12.656823
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

High resolution electron beam lithography poses severe constraints on any suitable resist, namely the need to work with very thin layers in order to achieve highest resolutions, while at the same time possessing suitable resistance to plasma etching. Small molecular sizes are also an interesting avenue for reducing line edge roughness, but result in an increased threshold exposure dose. Several resists currently available cover the range from high resolution to high sensitivity. One interesting property demonstrated using the QSR-5^TM resist is substrate conformability. This thermally evaporated resist has a controllable thickness down to 30 nm and surface roughness less than 2 nm and can be deposited onto very small surfaces. In this paper, we will present the results of patterning this resist in a configuration which may be suitable for very high speed field effect devices. A silicon nitride membrane 300 nm thick was prepared on a silicon substrate. QSR-5^TM resist is then deposited in two steps, using a Joule effect thermal evaporator with the resist in a powdered state. After a deposition of 30 nm of resist, the substrate is flipped over and a second identical layer is deposited. The membrane is removed from vacuum during the reversal process. The lithography step follows the deposition step and is carried out using a field emission gun SEM converted to electron beam lithography operated at a beam energy of 20 keV. Test patterns with feature sizes ranging from 45 nm to 130 nm were successfully exposed. The advantage of this method is that perfect alignment between the patterns is obtained on both sides of the resist.

Citation Download Citation

Jacques Beauvais, Prasad Kelkar, Eric Lavallée, Dominique Drouin, and Kien Mun Lau "Self-aligned direct write of a double-sided transistor gate on membrane using an evaporated e-beam resist", Proc. SPIE 6153, Advances in Resist Technology and Processing XXIII, 615348 (29 March 2006); https://doi.org/10.1117/12.656823

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KEYWORDS

Silicon

Electron beam lithography

Chromium

Monte Carlo methods

Electron beams

Transistors

Silicon films

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