Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Jae-Hyun Kang; Jae-Young Choi; Kyung-Hee Yun; Munho Do; Yong-Suk Lee; Keeho Kim

doi:10.1117/12.657050

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20 March 2006 Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Jae-Hyun Kang, Jae-Young Choi, Kyung-Hee Yun, Munho Do, Yong-Suk Lee, Keeho Kim

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Proceedings Volume 6154, Optical Microlithography XIX; 61543J (2006) https://doi.org/10.1117/12.657050
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

Optical Proximity Correction (OPC) often reaches its limitation, especially low-k imaging. It results in yield drop by bridging, pinching, and other process window sensitive issues. It happens more when the original layout contains OPC-unfriendly patterns. With OPC-unfriendly layout, OPC model generates totally unexpected results such as narrow space, small jog, small serif and etc. Those unexpected OPC results induce bridged patterns as well as narrow process margin. And they will give direct yield loss of device. Thus, it is critical to implement the flow for Litho Friendly Design (LFD) and nevertheless simulation-based OPC verification. In this study, a new approach of OPC has been tested, which contains the simulation based analysis of OPC failure and in turn out reconstruct OPC features in a way to fix not only bridging and pinching but also to improve process window. This proves to reduce mask respin by 50% or more. It also has been tried to be a complementary checking in addition to conventional CD monitor in pilot production.

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Jae-Hyun Kang, Jae-Young Choi, Kyung-Hee Yun, Munho Do, Yong-Suk Lee, and Keeho Kim "Simulation based post OPC verification to enhance process window, critical failure analysis, and yield", Proc. SPIE 6154, Optical Microlithography XIX, 61543J (20 March 2006); https://doi.org/10.1117/12.657050

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