Layout verification and optimization based on flexible design rules

Jie Yang; Luigi Capodieci; Dennis Sylvester

doi:10.1117/12.658982

24 March 2006 Layout verification and optimization based on flexible design rules

Jie Yang, Luigi Capodieci, Dennis Sylvester

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 61560A (2006) https://doi.org/10.1117/12.658982
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

A methodology for layout verification and optimization based on exible design rules is provided. This methodology is based on image parameter determined exible design rules (FDRs), in contrast with restrictive design rules (RDRs), and enables fine-grained optimization of designs in the yield-performance space. Conventional design rules are developed based on experimental data obtained from design, fabrication and measurements of a set of test structures. They are generated at early stage of a process development and used as guidelines for later IC layouts. These design rules (DRs) serve to guarantee a high functional yield of the fabricated design. Since small areas are preferred in integrated circuit designs due to their corresponding high speed and lower cost, most design rules focus on minimum resolvable dimensions.

Citation Download Citation

Jie Yang, Luigi Capodieci, and Dennis Sylvester "Layout verification and optimization based on flexible design rules", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560A (24 March 2006); https://doi.org/10.1117/12.658982

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