Paper
13 March 2006 Hot spot management in ultra-low k1 lithography
Author Affiliations +
Abstract
We have constructed a hot spot management flow for LSI manufacturing in the ultra-low k1 lithography era. This flow involves three main management steps: hot spot reduction, hot spot extraction and hot spot monitoring. Hot spot reduction works for lithography friendly restriction (RDR) and manufacturability check (MC). Hot spot extraction is carried out with consideration of short turn-around-time (TAT), accurate extraction and convenient functions such as hot spot for interlayers. Hot spot monitoring is achieved with tolerance-based verification in mask fabrication process and wafer process (lithography and etching). These technology elements were integrated into the actual LSI fabrication flow. The application of this concept to LSI manufacturing could contribute to reduction of total cost, quick TAT and ramp up to volume production.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kohji Hashimoto, Satoshi Usui, Shigeki Nojima, Satoshi Tanaka, Eiji Yamanaka, and Soichi Inoue "Hot spot management in ultra-low k1 lithography", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560N (13 March 2006); https://doi.org/10.1117/12.656418
Lens.org Logo
CITATIONS
Cited by 6 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Tolerancing

Lithography

Semiconducting wafers

Photomasks

Manufacturing

Feature extraction

Optical proximity correction

RELATED CONTENT

Verifying RET mask layouts
Proceedings of SPIE (July 12 2002)
Improved manufacturability by OPC based on defocus data
Proceedings of SPIE (July 10 2003)
SEMATECH J111 project: OPC validation
Proceedings of SPIE (June 29 1998)

Back to Top