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14 March 2006 Full-chip lithography manufacturability check for yield improvement
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In this paper, we will demonstrate a novel approach to improve process window prediction capability. The new method, Lithography Manufacturability Check (LMC), will be shown to be capable of predicting wafer level CDs across an entire chip and the lithography process window with a CD accuracy of better than 10nm. The impact of reticle CD error on the weak points also will be discussed. The advantages of LMC for full chip process window analysis as well as the MEEF check to catch process weak points will be shown and the application to real designs will be demonstrated in this paper. LMC and MEEF checks are based on a new lithography model referred to as the Focus Exposure Matrix Model (FEM Model). Using this approach, a single model capable of simulating a complete range of focus and exposure conditions can be generated with minimal effort. Such models will be shown to achieve a predictive accuracy of less than 5nm for device patterns at nominal conditions and less than 10nm across the entire range of process conditions which define the nominal process window. Based on the inspection results of the full chip LMC check, we identify process weak points (with limited process window or excessive sensitivity to mask error) and provide feedback to the front end design stage for pattern correction to maximize the overall process window and increase production manufacturability. The performance and full function of LMC will also be described in this paper.
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Yongfa Huang, Edward Tseng, Benjamin Szu-Min Lin, Chun Chi Yu, Chien-Ming Wang, and Hua-Yu Liu "Full-chip lithography manufacturability check for yield improvement", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560W (14 March 2006);

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