Paper
26 April 2006 System Verilog modelling of FIR filters
Łukasz Pawlus, Marek Wegrzyn
Author Affiliations +
Proceedings Volume 6159, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV; 61590G (2006) https://doi.org/10.1117/12.674858
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV, 2005, Wilga, Poland
Abstract
In the paper modelling of FIR filters by means of Verilog and SystemVerilog is presented. Hardware/software co-design approach for such systems is applied in the presented design. As a final technology for a FIR filters system implementation, a FPSLIC device is considered. Filters system demonstrates example methods of communication between FPGA and AVR microcontroller in a FPSLIC structure, i.e. the communication through SRAM memory, addressing lines, data bus, interrupts. It also demonstrates how to serve peripheral elements in FPSLIC device by means of DPI interface. FIR filters model contains also interface which implements a FPSLIC cache logic and gives opportunity to a dynamical reconfiguration of FPGA in a FPSLIC structure.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Łukasz Pawlus and Marek Wegrzyn "System Verilog modelling of FIR filters", Proc. SPIE 6159, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV, 61590G (26 April 2006); https://doi.org/10.1117/12.674858
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KEYWORDS
Finite impulse response filters

Field programmable gate arrays

Telecommunications

Modeling

Systems modeling

Logic

Microcontrollers

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