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7 September 2006 CMOS minimal array
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Abstract
A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James Janesick, John Cheng, Jeanne Bishop, James T. Andrews, John Tower, Jeff Walker, Mark Grygon, and Tom Elliot "CMOS minimal array", Proc. SPIE 6295, Infrared Detectors and Focal Plane Arrays VIII, 62950O (7 September 2006); https://doi.org/10.1117/12.693204
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