Translator Disclaimer
Paper
20 October 2006 Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20
Author Affiliations +
Abstract
In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows. The approach does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking. A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown. Lithography results are shown with effective k1<0.2 for logic and flash memory patterns.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Judy Huckabay, Wolf Staud, Robert Naber, Anton van Oosten, Peter Nikolski, Stephen Hsu, R. J. Socha, M. V. Dusa, and Donis Flagello "Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20", Proc. SPIE 6349, Photomask Technology 2006, 634910 (20 October 2006); https://doi.org/10.1117/12.687747
PROCEEDINGS
11 PAGES


SHARE
Advertisement
Advertisement
Back to Top