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20 October 2006 A novel approach for hot-spot removal for sub-100nm manufacturing
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Recent advances in lithography simulation have made full-chip lithography rule checking (LRC) practical and even mandatory for many fabs, especially those operating with half-pitches under 100nm. These LRCs routinely identify marginal or even fatal manufacturability problems (hot-spots), especially when simulated through process corners. Until recently, when hot-spots were identified, the only options were to reject the tapeout for additional layout modifications, re-run OPC with a different recipe, or use a DRC-tool to do "blind" cut-and-paste repairs under the assumption that making fatal errors non-fatal is sufficient to make them "good." Using a commercial LRC tool, we will inspect OPC data on a production design to identify a typical volume of real and potential hot-spots. Next, using Halo-Fix from Aprio Technologies, we will apply local repairs, choosing rule-based or model-based repair strategies as appropriate for each type of hot-spot. Using this method, "intelligent" changes in the hot-spot areas can be made which accurately account for lithography interactions and process variations, in order to optimize for manufacturing robustness. To verify that the repairs are acceptable, LRCs will be performed and the results analyzed.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Melody Ma, Melissa Anderson, Weinong Lai, Clive Wu, Becky Tsao, Chih-wei Chu, Char Lin, Jacky Chou, and Sidney Tsai "A novel approach for hot-spot removal for sub-100nm manufacturing", Proc. SPIE 6349, Photomask Technology 2006, 63492P (20 October 2006);

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