Paper
5 April 2007 Characterization of line-edge roughness in Cu/low-k interconnect pattern
Atsuko Yamaguchi, Daisuke Ryuzaki, Jiro Yamamoto, Hiroki Kawada, Takashi Iizumi
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Abstract
To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The maximum electric-field intensity depends upon the conventional LER metric, 3Rq, but depends more strongly on the wedge angle, the curvature of the tip, and the minimum linewidth.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Atsuko Yamaguchi, Daisuke Ryuzaki, Jiro Yamamoto, Hiroki Kawada, and Takashi Iizumi "Characterization of line-edge roughness in Cu/low-k interconnect pattern", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65181P (5 April 2007); https://doi.org/10.1117/12.710401
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Cited by 8 scholarly publications.
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KEYWORDS
Line edge roughness

Copper

Line width roughness

Semiconducting wafers

Dielectrics

Diffusion

Metals

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