Impact of line-width roughness on Intel’s 65-nm process devices

Manish Chandhok; Suman Datta; Daniel Lionberger; Scott Vesecky

doi:10.1117/12.712955

22 March 2007 Impact of line-width roughness on Intel's 65-nm process devices

Manish Chandhok, Suman Datta, Daniel Lionberger, Scott Vesecky

Proceedings Volume 6519, Advances in Resist Materials and Processing Technology XXIV; 65191A (2007) https://doi.org/10.1117/12.712955
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Line Width Roughness (LWR) is the random variation of MOS gate length along the gate width. LWR is undesirable because it degrades drive current (Ion), increases off-current (Ioff), and causes a random variation of device parameters across a die. Previously, it was determined that LWR did not impact Intel's 130 nm process devices. As device sizes shrink, the sensitivity to LWR increases, so the amount of LWR that can be tolerated in future generations needs to be re-assessed. In this paper we will present the experimental results of the effects of LWR on Intel's 65 nm process. It was found that both nominal drive current and its variation degrade with increased LWR. Additionally, Ioff increased exponentially with increased LWR. In order to maintain less than 2% degradation in Ion from LWR, the 3-Sigma % LWR should be less than 10% of the nominal final check critical dimension (FCCD). Thus, for future generations, LWR needs to scale as gate lengths decrease or else any potential benefits in increased drive current would be offset by large amounts of leakage.

Citation Download Citation

Manish Chandhok, Suman Datta, Daniel Lionberger, and Scott Vesecky "Impact of line-width roughness on Intel's 65-nm process devices", Proc. SPIE 6519, Advances in Resist Materials and Processing Technology XXIV, 65191A (22 March 2007); https://doi.org/10.1117/12.712955

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