Integrating immersion lithography in 45-nm logic manufacturing

Michael Benndorf; Scott Warrick; Will Conley; David Cruau; Danilo DeSimone; Karim Mestadi; Vincent Farys; Jan-Willem Gemmink

doi:10.1117/12.715987

27 March 2007 Integrating immersion lithography in 45-nm logic manufacturing

Michael Benndorf, Scott Warrick, Will Conley, David Cruau, Danilo DeSimone, Karim Mestadi, Vincent Farys, Jan-Willem Gemmink

Author Affiliations +

Proceedings Volume 6520, Optical Microlithography XX; 652007 (2007) https://doi.org/10.1117/12.715987
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Semiconductor manufacturers work hard to shrink critical dimensions in their device architectures and are in the midst of the 45nm node development. Generally, for the 65nm node, critical layers are processed using 193-nm scanners with numerical apertures up to 0.85 and non-immersion technology. It is clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) need to be examined, especially as the industry turns its attention towards the 45-nm technology generation. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. In this paper, we report on the progress of development for the 45nm device level lithography with imaging systems >1NA at the Crolles 2 Alliance. Our continued focus is the insertion of an immersion lithography process into an established pilot manufacturing line to support 45nm process development. We will present immersion resist performance, OPC feasibility, process integration, and defectivity comparisons. Finally, conclusions will be made as to the overall readiness of immersion to support 45nm node processing.

Citation Download Citation

Michael Benndorf, Scott Warrick, Will Conley, David Cruau, Danilo DeSimone, Karim Mestadi, Vincent Farys, and Jan-Willem Gemmink "Integrating immersion lithography in 45-nm logic manufacturing", Proc. SPIE 6520, Optical Microlithography XX, 652007 (27 March 2007); https://doi.org/10.1117/12.715987

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KEYWORDS

Semiconducting wafers

Immersion lithography

Critical dimension metrology

Scanners

Manufacturing

Source mask optimization

Overlay metrology

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