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21 March 2007 Self-assembled dummy patterns for lithography process margin enhancement
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Over the last couple of years, Design For Manufacturability (DFM) has progressed from concept to practice. What we thought then is actually applied to the design step to meet the high demand placed upon very high tech devices we make today. One of the DFM procedures that benefit the lithography process margin is generation of dummy patterns. Dummy pattern generated at design step enables stable yet high lithography process margin for many of the high technology device. But actual generation of the dummy pattern is very complex and risky for many of the layer used for memory devices. Dummy generation for simple pattern layers such as Poly or Isolation layer is not so difficult since pattern composed for these layers are usually 1 dimensional or very simple 2 dimensional patterns. But for interconnection layers that compose of complex 2 dimensional patterns, dummy pattern generation is very risky and requires lots of time and effort to safely place the dummy patterns. In this study, we propose simple self assembled dummy (SAD) generation algorithm to place dummy pattern for the complex 2 dimensional interconnection layers. This algorithm automatically self assembles dummy pattern based on the original design layout, therefore insuring the safety and simplicity of the generated dummy to the original design. Also we will evaluate SAD on interconnection layer using commercial Model Based Verification (MBV) tool to verify its applicability for both litho process margin and DFM perspective.
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James Moon, Byoung-Sub Nam, Joo-Hong Jeong, Byung-Ho Nam, and Dong Gyu Yim "Self-assembled dummy patterns for lithography process margin enhancement", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652118 (21 March 2007);


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