High-level power estimation for digital system

Yaseer A. Durrani; Ana Abril; Teresa Riesgo

doi:10.1117/12.721182

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10 May 2007 High-level power estimation for digital system

Yaseer A. Durrani, Ana Abril, Teresa Riesgo

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Proceedings Volume 6590, VLSI Circuits and Systems III; 659002 (2007) https://doi.org/10.1117/12.721182
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

In this paper, we present a high-level power macromodeling technique at register transfer level (RTL). The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) macro-blocks by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

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Yaseer A. Durrani, Ana Abril, and Teresa Riesgo "High-level power estimation for digital system", Proc. SPIE 6590, VLSI Circuits and Systems III, 659002 (10 May 2007); https://doi.org/10.1117/12.721182

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