Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture

S. López; A. Kanstein; J. F. López; M. Berekovic; R. Sarmiento; J.-Y. Mignolet

doi:10.1117/12.722042

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10 May 2007 Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture

S. López, A. Kanstein, J. F. López, M. Berekovic, R. Sarmiento, J.-Y. Mignolet

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Proceedings Volume 6590, VLSI Circuits and Systems III; 65900A (2007) https://doi.org/10.1117/12.722042
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor.

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S. López, A. Kanstein, J. F. López, M. Berekovic, R. Sarmiento, and J.-Y. Mignolet "Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900A (10 May 2007); https://doi.org/10.1117/12.722042

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