A parallel architecture of interpolated timing recovery for high-speed data transfer rate and wide capture-range

Satoru Higashino; Shoei Kobayashi; Tamotsu Yamagami

doi:10.1117/12.738923

17 July 2007 A parallel architecture of interpolated timing recovery for high- speed data transfer rate and wide capture-range

Satoru Higashino, Shoei Kobayashi, Tamotsu Yamagami

Author Affiliations +

Proceedings Volume 6620, Optical Data Storage 2007; 66200Y (2007) https://doi.org/10.1117/12.738923
Event: Optical Data Storage 2007, 2007, Portland, OR, United States

Abstract

High data transfer rate has been demanded for data storage devices along increasing the storage capacity. In order to increase the transfer rate, high-speed data processing techniques in read-channel devices are required. Generally, parallel architecture is utilized for the high-speed digital processing. We have developed a new architecture of Interpolated Timing Recovery (ITR) to achieve high-speed data transfer rate and wide capture-range in read-channel devices for the information storage channels. It facilitates the parallel implementation on large-scale-integration (LSI) devices.

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Satoru Higashino, Shoei Kobayashi, and Tamotsu Yamagami "A parallel architecture of interpolated timing recovery for high- speed data transfer rate and wide capture-range", Proc. SPIE 6620, Optical Data Storage 2007, 66200Y (17 July 2007); https://doi.org/10.1117/12.738923

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