As part of the technical program in Photomask Japan 2007, we held a panel discussion to discuss challenges and
solutions for the double exposure and double patterning lithography technique for 32nm half-pitch design node. 4
panelists, Rik Jonckheere of IMEC (Belgium), Tsann-Binn Chiou of ASML Taiwan Ltd. (Taiwan), Judy Huckabay of
Cadence Design Systems Inc. (USA) and Yoshimitsu Okuda of Toppan Printing Co., Ltd. (Japan) were invited to
represent each key technical area.
We also took a survey from the PMJ attendees prior to the panel discussion, to vote which key technical area they think
the challenge exists for the 32nm half-pitch DE/DP lithography. The result of the survey was also presented during the
One would intuitively think that by using a DE/DP technique you're relaxing the design rule by 2x, thus for 32nm node
it's essentially the 65nm process- you're just repeating it 2 times. Well, not exactly, as identified by the panelists and
the participants in the discussion. We recognized the difficulties in the LSI fabrication process steps, the lithography
tool overlay, photomask CD and registration, and the issue of data splitting conflict.
These difficulties are big challenge for both LSI and photomask manufactures; however, we have confirmed some
solutions are already examined by the theoretical and experimental works of the people in research. Despite these
difficulties, we are convinced that the immersion lithography with double exposure and double patterning techniques is
one of the most promising candidates of the lithography for 32nm half pitch design node.