A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL

Konstantinos Vitoroulis; Tadeusz Obuchowicz; Asim J. Al-Khalili

doi:10.1117/12.759454

21 December 2007 A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL

Konstantinos Vitoroulis, Tadeusz Obuchowicz, Asim J. Al-Khalili

Proceedings Volume 6798, Microelectronics: Design, Technology, and Packaging III; 67980Q (2007) https://doi.org/10.1117/12.759454
Event: SPIE Microelectronics, MEMS, and Nanotechnology, 2007, Canberra, ACT, Australia

Abstract

In this paper we present a CAD tool capable of generating a variety of parallel prefix adders described in the VHDL language. The VHDL code generated by the tool is synthesizable and the resulting adders can be used as design components in an automatic or semi-custom design flow. In its current version the tool is able to generate arbitrary bit-size prefix adders of the following types: Sklansky, Ladner-Fischer, Kogge-Stone, Han-Carlson, Brent-Kung and Knowles.

Citation Download Citation

Konstantinos Vitoroulis, Tadeusz Obuchowicz, and Asim J. Al-Khalili "A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL", Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980Q (21 December 2007); https://doi.org/10.1117/12.759454

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