Paper
11 January 2008 Effect of thermal stress and diameter on I-V characteristics of template synthesized Cu-Se heterostructures
S. K. Chakarvarti, Meeru Chaudhri
Author Affiliations +
Proceedings Volume 6800, Device and Process Technologies for Microelectronics, MEMS, Photonics, and Nanotechnology IV; 68001H (2008) https://doi.org/10.1117/12.759582
Event: SPIE Microelectronics, MEMS, and Nanotechnology, 2007, Canberra, ACT, Australia
Abstract
One-dimensional nanostructures, such as nano-wires and nano-belts, offer a high degree of interest for furthering the current state of nanotechnology research and development. Higher aspect ratio, diameter dependent band-gap, and increased surface scattering for electrons are some of the more significant features in which nano-wires differ from their normal counterparts, which exhibit bulk properties. Many methods for the fabrication of nano-wires, nano-rods and nano-tubes have been developed including lithographic and non-lithographic techniques. Among them Template synthesis (non-lithographic technique) is a versatile, flexible and simple approach to the fabrication of metallic nano-wires and nano-tubes. We have successfully fabricated arrays of Cu-Se 5μm, 1μm, 100nm, 40nm hetero structures using a non-lithographic technique of filling cylindrical pores of track-etch membranes with Cu and Se materials. These were then analyzed by scanning electron microscope. I-V curves of deposited Cu-Se hetero structures of varying diameters were also recorded which show increase of negative differential resistance with decrease in diameters of these hetero-structures. The effect of thermal annealing at different temperatures causing thermal stress on these synthesized structures was also studied.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. K. Chakarvarti and Meeru Chaudhri "Effect of thermal stress and diameter on I-V characteristics of template synthesized Cu-Se heterostructures", Proc. SPIE 6800, Device and Process Technologies for Microelectronics, MEMS, Photonics, and Nanotechnology IV, 68001H (11 January 2008); https://doi.org/10.1117/12.759582
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KEYWORDS
Nanowires

Thermal effects

Heterojunctions

Annealing

Fabrication

Nanolithography

Nanostructures

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