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12 February 2008 Monolithic integration of photonic and electronic circuits in a CMOS process
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We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Attila Mekis, Sherif Abdalla, Behnam Analui, Steffen Gloeckner, Andrew Guckenberger, Roger Koumans, Daniel Kucharski, Yi Liang, Gianlorenzo Masini, Sina Mirsaidi, Adithyaram Narasimha, Thierry Pinguet, Vikram Sadagopan, Brian Welch, Joe White, and Jeremy Witzens "Monolithic integration of photonic and electronic circuits in a CMOS process", Proc. SPIE 6897, Optoelectronic Integrated Circuits X, 68970L (12 February 2008);


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