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22 March 2008 Process control for 45 nm CMOS logic gate patterning
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Abstract
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bertrand Le Gratiet, Pascal Gouraud, Enrique Aparicio, Laurene Babaud, Karen Dabertrand, Mathieu Touchet, Stephanie Kremer, Catherine Chaton, Franck Foussadier, Frank Sundermann, Jean Massin, Jean-Damien Chapon, Maxime Gatefait, Blandine Minghetti, Jean de-Caunes, and Daniel Boutin "Process control for 45 nm CMOS logic gate patterning", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69220Z (22 March 2008); https://doi.org/10.1117/12.776889
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