Paper
24 March 2008 High order correction and sampling strategy for 45nm immersion lithography overlay control
Bo Yun Hsueh, George K. C. Huang, Chun-Chi Yu, Jerry K. C. Hsu, Chin-Chou Kevin Huang, Chien-Jen Huang, David Tien
Author Affiliations +
Abstract
As advanced semiconductor companies move forward to the 45nm technology node, traditional overlay sampling and linear correction used in dry lithography become less feasible to bring overlay control into the desired budget. New overlay control methodologies need to be established to meet the needs of much tighter overlay budgets in the immersion lithography process. Overlay source of variance (SOV) was first investigated to understand the major contributor of overlay error sources. The SOVis broken down into wafer, field, and random components in order to utilize the SOV information to prioritize overlay improvement decisions. High order wafer level or field level error components are commonly observed as a significant contributor and requires attention to bring the overlay residual into the desired limit. Optimal sample is determined in considering sample plan robustness and throughput impact while increasing sampling becomes a necessity in 45nm technology node.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bo Yun Hsueh, George K. C. Huang, Chun-Chi Yu, Jerry K. C. Hsu, Chin-Chou Kevin Huang, Chien-Jen Huang, and David Tien "High order correction and sampling strategy for 45nm immersion lithography overlay control", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69222Q (24 March 2008); https://doi.org/10.1117/12.772107
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CITATIONS
Cited by 10 scholarly publications and 2 patents.
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KEYWORDS
Semiconducting wafers

Overlay metrology

Data modeling

Statistical modeling

Immersion lithography

Scanners

Error analysis

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