Immersion resist process for 32-nm node logic devices

Tatsuhiko Ema; Koutaro Sho; Hiroki Yonemitsu; Yuriko Seino; Hiroharu Fujise; Akiko Yamada; Shoji Mimotogi; Yosuke Kitamura; Satoshi Nagai; Kotaro Fujii; Takashi Fukushima; Toshiaki Komukai; Akiko Nomachi; Tsukasa Azuma; Shinichi Ito

doi:10.1117/12.771008

31 March 2008 Immersion resist process for 32-nm node logic devices

Tatsuhiko Ema, Koutaro Sho, Hiroki Yonemitsu, Yuriko Seino, Hiroharu Fujise, Akiko Yamada, Shoji Mimotogi, Yosuke Kitamura, Satoshi Nagai, Kotaro Fujii, Takashi Fukushima, Toshiaki Komukai, Akiko Nomachi, Tsukasa Azuma, Shinichi Ito

Author Affiliations +

Proceedings Volume 6923, Advances in Resist Materials and Processing Technology XXV; 69230E (2008) https://doi.org/10.1117/12.771008
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the critical layers according to the substrate transparency. Another key issue in terms of material process was described in this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA immersion lithography and pattern transfer performance using single BARC

Citation Download Citation

Tatsuhiko Ema, Koutaro Sho, Hiroki Yonemitsu, Yuriko Seino, Hiroharu Fujise, Akiko Yamada, Shoji Mimotogi, Yosuke Kitamura, Satoshi Nagai, Kotaro Fujii, Takashi Fukushima, Toshiaki Komukai, Akiko Nomachi, Tsukasa Azuma, and Shinichi Ito "Immersion resist process for 32-nm node logic devices", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 69230E (31 March 2008); https://doi.org/10.1117/12.771008

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