Paper
15 April 2008 Wafer shape compensation at the track PEB for improved CD uniformity
Timothy Michaelson, Junyan Dai, Lu Chen, Hiram Cervera, Brian Lue, Harald Herchen, Kim Vellore, Nikolaos Bekiaris
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Abstract
This paper investigates the feasibility of using an electrostatic chuck (ESC) on a post exposure bake (PEB) plate in the track to improve the critical dimension uniformity (CDU) for bowed wafers. Although it is more conventional to consider vacuum chucking during PEB, electrostatic chucking offers some potential advantages, chief among which is the fact that electrostatic chucking does not require any type of a seal between the wafer and the PEB plate whereas vacuum chucking does. Such a seal requires contact and therefore has the potential to generate backside particles on the wafer. Electrostatic chucking therefore has the potential for a cleaner overall process. Three different PEB plates were tested in the course of this investigation, a non-chucking PEB plate (SRHP), a PEB plate equipped with a vacuum chuck (VRHP), and a PEB plate equipped with an ESC (eBHP). It was found that CD uniformities were up to 84 percent lower for bowed wafers that were chucked during PEB relative to wafers that were not chucked. In every case tested, wafers processed through chucking PEB plates showed lower CDUs than wafers processed through the non-chucking plate. CDU results were similar between vacuum chucked wafers and electrostatic chucked wafers. Based on the results presented in this paper, it can be concluded that electrostatic chucking during PEB is a feasible method for controlling CD uniformities on bowed wafers.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Timothy Michaelson, Junyan Dai, Lu Chen, Hiram Cervera, Brian Lue, Harald Herchen, Kim Vellore, and Nikolaos Bekiaris "Wafer shape compensation at the track PEB for improved CD uniformity", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 69233M (15 April 2008); https://doi.org/10.1117/12.772894
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KEYWORDS
Semiconducting wafers

Critical dimension metrology

Particles

Lithography

Scanners

Scanning electron microscopy

Wafer testing

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