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In June 2007, Intel announced a new pixelated mask technology. This technology was created to address the problem
caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has
increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction (OPC) was
introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of
techniques to maintain image quality. The computational lithography group at Intel sought to alleviate this problem by
experimenting with additional degrees of freedom within the mask. This paper describes the resulting pixelated mask
technology, and some of the computational methods used to create it. The first key element of this technology is a thick
mask model. We realized very early in the development that, unlike traditional OPC methods, the pixelated mask would
require a very accurate thick mask model. Whereas in the traditional methods, one can use the relatively coarse
approximations such as the boundary layer method, use of such techniques resulted not just in incorrect sizing of parts of
the pattern, but in whole features missing. We built on top of previously published domain decomposition methods, and
incorporated limitations of the mask manufacturing process, to create an accurate thick mask model. Several additional
computational techniques were invoked to substantially increase the speed of this method to a point that it was feasible
for full chip tapeout. A second key element of the computational scheme was the comprehension of mask
manufacturability, including the vital issue of the number of colors in the mask. While it is obvious that use of three or
more colors will give the best image, one has to be practical about projecting mask manufacturing capabilities for such a
complex mask. To circumvent this serious issue, we eventually settled on a two color mask - comprising plain glass and
etched glass. In addition, there were several smaller manufacturability concerns, for example a "1X1" glass pillar (an
isolated 0 phase pixel) were susceptible to collapse under the stress of mask processing, and therefore these had to be
constrained out of the final configuration. A third key element was defining the objective function. We experimented
with a large number of choices and eventually settled on a form that allows us to trade-off fidelity and contrast. A fourth
key element was the optimization algorithm. The number of possible configurations for a trillion pixels present on our
final product mask is greater than the number of total elementary particles in the known universe, so finding the
proverbial needle in this haystack was difficult to say the least. We chose a mixture of stochastic and direct descent
algorithms to find an arrangement that meets the demands. While we have not proved we are close to the absolute global
minimum, we conducted several experiments to suggest this is the case. A fifth key element, and a large one at that, was
scaling up our software system from micron length scale to centimeter length scale required for full chip tapeout. This
software, in turn, has several key components - hierarchy handling, the non-trivial handling of pixelated domain
boundaries, repair of regions not converged in terms of image quality, and verification of the entire assembled database.
All elements described above were validated through the tapeout of an actual mask to pattern the most complex metal
layer for the leading 65nm node microprocessor in high volume manufacturing. This very first experimental tapeout
resulted in wafer parts yield comparable to yields on mass produced wafers made with production 65nm technology.
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