Paper
7 March 2008 32nm overlay improvement capabilities
Author Affiliations +
Abstract
The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control. Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning lithography is an approach that's being considered for 32 and below, but it creates very strict demands for overlay performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in extremely tight tolerances for overlay error and scanner capabilities. The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node. Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of current scanner performance and project the anticipated improvements from our new modeling approach. Since the new modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of such approach.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Brad Eichelberger, Kevin Huang, Kelly O'Brien, David Tien, Frank Tsai, Anna Minvielle, Lovejeet Singh, and Jeffrey Schefske "32nm overlay improvement capabilities", Proc. SPIE 6924, Optical Microlithography XXI, 69244C (7 March 2008); https://doi.org/10.1117/12.773014
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CITATIONS
Cited by 11 scholarly publications.
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KEYWORDS
Semiconducting wafers

Scanners

Overlay metrology

Metrology

Double patterning technology

Performance modeling

Data modeling

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