Paper
4 March 2008 Effective learning and feedback to designers through design and wafer inspection integration
Crockett Huang, Hermes Liu, S. F. Tzou, Allen Park, Chris Young, Ellis Chang
Author Affiliations +
Abstract
As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Crockett Huang, Hermes Liu, S. F. Tzou, Allen Park, Chris Young, and Ellis Chang "Effective learning and feedback to designers through design and wafer inspection integration", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692506 (4 March 2008); https://doi.org/10.1117/12.772242
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CITATIONS
Cited by 3 scholarly publications.
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KEYWORDS
Semiconducting wafers

Data modeling

Inspection

Metrology

Finite element methods

Optical proximity correction

Defect inspection

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