Electrical metrics for lithographic line-end tapering

Puneet Gupta; Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park

doi:10.1117/12.793117

19 May 2008 Electrical metrics for lithographic line-end tapering

Puneet Gupta, Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park

Proceedings Volume 7028, Photomask and Next-Generation Lithography Mask Technology XV; 70283A (2008) https://doi.org/10.1117/12.793117
Event: Photomask and NGL Mask Technology XV, 2008, Yokohama, Japan

Abstract

A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the I_on and I_off impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ΔI_on and ΔI_off. Finally, the electrical metric for line-end printing is defined as expected change in I_on or I_off under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

Citation Download Citation

Puneet Gupta, Kwangok Jeong, Andrew B. Kahng, and Chul-Hong Park "Electrical metrics for lithographic line-end tapering", Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70283A (19 May 2008); https://doi.org/10.1117/12.793117

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