Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Alexander Tritchkov; Petr Glotov; Sergiy Komirenko; Emile Sahouria; Andres Torres; Ahmed Seoud; Vincent Wiaux

doi:10.1117/12.801381

17 October 2008 Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Alexander Tritchkov, Petr Glotov, Sergiy Komirenko, Emile Sahouria, Andres Torres, Ahmed Seoud, Vincent Wiaux

Author Affiliations +

Proceedings Volume 7122, Photomask Technology 2008; 71220S (2008) https://doi.org/10.1117/12.801381
Event: SPIE Photomask Technology, 2008, Monterey, California, United States

Abstract

Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis. In particular, the methodology contains: - A DRC-like layout DP compliance and design verification functions; - A parameterization scheme that codifies manufacturing knowledge and capability; - Judicious use of physical effect simulation to improve double-patterning quality; - An efficient, high capacity mask synthesis function for post-tapeout processing; - A verification function to determine the correctness and qualify of a DP solution; Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch (LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in multiple exposure processed in the same resist layer. The theoretical k₁ for a double-patterning technology applied to a 32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k₁ for a single-patterning of this same design would be 0.22 [2], which is sub-resolution. This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also demonstrates verification solution implementation in the chip design flow and post-tapeout flow.

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Alexander Tritchkov, Petr Glotov, Sergiy Komirenko, Emile Sahouria, Andres Torres, Ahmed Seoud, and Vincent Wiaux "Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp", Proc. SPIE 7122, Photomask Technology 2008, 71220S (17 October 2008); https://doi.org/10.1117/12.801381

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