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Programmed defect test masks serve the useful purpose of evaluating inspection system sensitivity and capability. It is
widely recognized that when evaluating inspection system capability, it is important to understand the actual sensitivity
of the inspection system in production; yet unfortunately we have observed that many test masks are a more accurate
judge of theoretical sensitivity rather than real-world usable capability. Use of ineffective test masks leave the purchaser
of inspection equipment open to the risks of over-estimating the capability of their inspection solution and overspecifying
defect sensitivity to their customers. This can result in catastrophic yield loss for device makers. In this paper
we examine some of the lithography-related technology advances which place an increasing burden on mask inspection
complexity, such as MEEF, defect printability estimation, aggressive OPC, double patterning, and OPC jogs. We
evaluate the key inspection system component contributors to successful mask inspection, including what can "go
wrong" with these components. We designed and fabricated a test mask which both (a) more faithfully represents actual
production use cases; and (b) stresses the key components of the inspection system. This mask's patterns represent
32nm, 36nm, and 45nm logic and memory technology including metal and poly like background patterns with
programmed defects.
This test mask takes into consideration requirements of advanced lithography, such as MEEF, defect printability, assist
features, nearly-repetitive patterns, and data preparation. This mask uses patterns representative of 32nm, 36nm, and
45nm logic, flash, and DRAM technology. It is specifically designed to have metal and poly like background patterns
with programmed defects. The mask is complex tritone and was designed for annular immersion lithography.
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