32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography

Robert T. Greenway; Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park; John S. Petersen

doi:10.1117/12.801883

17 October 2008 32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography

Robert T. Greenway, Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, John S. Petersen

Author Affiliations +

Proceedings Volume 7122, Photomask Technology 2008; 71221L (2008) https://doi.org/10.1117/12.801883
Event: SPIE Photomask Technology, 2008, Monterey, California, United States

Abstract

As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

Citation Download Citation

Robert T. Greenway, Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, and John S. Petersen "32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography", Proc. SPIE 7122, Photomask Technology 2008, 71221L (17 October 2008); https://doi.org/10.1117/12.801883

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