DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization

Chung-Min Fu; Ping-Heng Yeh; Yi-Kan Cheng; Simon Klaver

doi:10.1117/12.802244

17 October 2008 DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization

Chung-Min Fu, Ping-Heng Yeh, Yi-Kan Cheng, Simon Klaver

Author Affiliations +

Proceedings Volume 7122, Photomask Technology 2008; 71221Z (2008) https://doi.org/10.1117/12.802244
Event: SPIE Photomask Technology, 2008, Monterey, California, United States

Abstract

Design-for-manufacturing (DFM) is becoming an actual design practice among IC manufacturers, designers and EDA companies. Layout assessment by design-rule-check (DRC) using EDA tools is a common practice today to ensure well-manufactured design geometries. Standalone DFM tools, which require iteration loops of DFM analysis and fixing, do not fit well in design flows and are considered cumbersome. A better layout assessment method for DFM issues is required: one that gives actionable feedback, and that can be used with automatic optimization in early design stages. The latter is needed to avoid costly design re-spins that will consume critical time-to-market as well as use a lot of engineering resources, reticles and wafer material costs. For example, a DFM checking tool may report the hotspot types and locations, but this information is not sufficient for designers to decide tradeoffs between different fixing choices and to take care of trade-off between physical and electrical design constraints at the same time. When model-based properties are introduced such as lithographic contour, the tradeoffs between rule-based and model-based properties can only be resolved by the automatic and concurrent optimization. This work demonstrates a methodology of DFM scoring of layout based on preferred rules compliance, lithography GATE printability, as well as the layout fixing. The electrical impact on gates is analyzed and showed reduced variability (compared to nominal behavior) in gate performance. Designers can get visual feedback of the layout quality, as well as improvement suggestions. Takumi TKE software is used to demonstrate automatic and concurrent optimization. The method applies to both cell-level and custom designs.

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Chung-Min Fu, Ping-Heng Yeh, Yi-Kan Cheng, and Simon Klaver "DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization", Proc. SPIE 7122, Photomask Technology 2008, 71221Z (17 October 2008); https://doi.org/10.1117/12.802244

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