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11 November 2008 Design of sparse mesh for optical network on chip
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Proceedings Volume 7136, Optical Transmission, Switching, and Subsystems VI; 71362F (2008)
Event: Asia-Pacific Optical Communications, 2008, Hangzhou, China
Nanoscale CMOS technologies are posing new network on chip concepts to IC designers. However, the electronic network on chip design faces many problems like energy consumption, long delay and limited bandwidth. Hence, optical network on chip appears as a good candidate to solve these problems. The advances in nanophotonic technology make it more realistic. A new sparse mesh is proposed for optical network on chip. Two types of non-blocking optical node architecture are also proposed to build up core node and switch node. The new architecture fully utilizes the property of XY routing in 2D mesh network, thus saving the number of microring resonators used. The comparisons are made with traditional mesh in number of microring resonators, loss and energy. The results show that the proposed sparse mesh achieves the best in all the aspects. For example, it uses 68% less number of resonators than the traditional mesh. We simulated 2D sparse mesh optical network on chip, and showed network performance under different traffic loads and data sizes. The results show sparse mesh achieves lower average delay and higher throughput than the traditional mesh.
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Huaxi Gu, Jiang Xu, and Zheng Wang "Design of sparse mesh for optical network on chip", Proc. SPIE 7136, Optical Transmission, Switching, and Subsystems VI, 71362F (11 November 2008);

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