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4 December 2008 Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies
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Proceedings Volume 7140, Lithography Asia 2008; 71401Z (2008)
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan
When k1 is smaller than the resolution limit, e.g., for a half-pitch (HP) ≤32nm, the most advanced immersion scanner does not have sufficient imaging capability. Extreme ultraviolet (EUV) technology at wavelength of 13.5nm is considered a practical light source for next-generation lithographic technology [1,2]. However, before EUV lithography is suited to mass production, an appropriate exposure technology is needed to fill the gap between immersion ArF and EUV scanners. Double patterning technology (DPT) is a technology that extends the usability of immersion ArF systems. Notably, DPT relaxes the minimum pitch of a circuit layout for each split exposure; thus, ArF water-based immersion systems can be extended to 32 nm node and beyond. Improvements to exposure system hardware are needed to enhance imaging, overlay, and productivity performance. Additionally, patterning-related processes [3-5] must be improved to ensure patterning fidelity when two splits are combined. The remaining challenge is to develop an intelligent approach for splitting the original layout to two different exposure mask layouts. Generally, DPT can be categorized as two types according to its applications. One type is the so-called 'litho DPT,' which adopts dual litho-etching steps. The final pattern is a combination of two individual litho-etched patterns. In this case, a normal pattern-splitting method is required to keep the minimum HP of separate patterns as large as possible. The best method for pattern splitting is to use a rule-based approach, which separates features according to their geometrical information such as edge-to-edge and/or vertex-to-vertex distance. When using a rule-based scheme, a full-chip pattern decomposition is practical because it can has fast processing speed. The other type is 'spacer DPT,' which adopts a single split pattern as a sacrificial layer to form spacers deposited onto pattern edges. The idea implies that one can arbitrarily select one of the split layouts. However, a normal pattern-splitting technique is still required. With the assistance of polygon Boolean operations, the trim layout (to remove residual polygons) and makeup layout (to repair irregular missing polygons) can be generated using scripting electronic design automation (EDA) software. In this study, some examples of pattern splitting are demonstrated using the Tachyon pattern-splitting tool. Furthermore, Tachyon scripts are utilized to create layouts with consideration of OPC for spacer DPT. The patterns created after each process step can be emulated with the scripts to help the process verification. All techniques developed in this study for DPT pattern splitting are applicable for 32nm node and beyond.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tsann-Bim Chiou, Robert Socha, Ho-Young Kang, Alek C. Chen, Stephen Hsu, Hong Chen, and Luoqi Chen "Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies", Proc. SPIE 7140, Lithography Asia 2008, 71401Z (4 December 2008);


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