Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder

Thomas Horvath; Da-ke He

doi:10.1117/12.805962

5 February 2009 Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder

Thomas Horvath, Da-ke He

Proceedings Volume 7244, Real-Time Image and Video Processing 2009; 724407 (2009) https://doi.org/10.1117/12.805962
Event: IS&T/SPIE Electronic Imaging, 2009, San Jose, California, United States

Abstract

Wyner-Ziv based video codecs reverse the processing complexity between encoders and decoders such that the complexity of the encoder can be significantly reduced at the expense of highly complex decoders requiring hardware accelerators to achieve real time performance. In this paper we describe a flexible hardware architecture for processing the Belief Propagation algorithm in a real time Wyner-Ziv video decoder for several hundred, very large, Low Density Parity Check (LDPC) codes. The proposed architecture features a hierarchical memory structure to provide a caching capability to overcome the high memory bandwidths needed to supply data to the processors. By taking advantage of the deterministic nature of LDPC codes to increase cache utilization, we are able to substantially reduce the size of expensive, high speed memory needed to support the processing of large codes compared to designs implementing a single layer memory structure.

Citation Download Citation

Thomas Horvath and Da-ke He "Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder", Proc. SPIE 7244, Real-Time Image and Video Processing 2009, 724407 (5 February 2009); https://doi.org/10.1117/12.805962

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