Optimization of photodetector thickness in vertically-integrated image sensors

Orit Skorka; Dan Sirbu; Dileepan Joseph

doi:10.1117/12.805999

27 January 2009 Optimization of photodetector thickness in vertically-integrated image sensors

Orit Skorka, Dan Sirbu, Dileepan Joseph

Proceedings Volume 7249, Sensors, Cameras, and Systems for Industrial/Scientific Applications X; 72490O (2009) https://doi.org/10.1117/12.805999
Event: IS&T/SPIE Electronic Imaging, 2009, San Jose, California, United States

Abstract

There is an emerging interest in vertically-integrated CMOS (VI-CMOS) image sensors. This trend arises from the difficulty in achieving high SNR, high dynamic range, and high frame rate with planar technologies while maintaining small pixel sizes, since the photodetector and electronics have to share the same pixel area and use the same technology. Fabrication methods for VI-CMOS image sensors add new degrees of freedom to the photodetector design. Having a model that gives a good approximation to the behavior of a device under different operating conditions is important for device optimization. This work presents a new approach in photodetector modeling, and uses it to optimize the thickness of the photosensitive layer in VI-CMOS image sensors. We consider a simplified structure of an a-Si:H photodetector, and develop an analytical solution and a numerical solution to state equations taken from semiconductor physics, which are shown to be comparable. If the photosensitive layer is too thin, our model shows that the contact resistances dominate the device and, if it is too thick, most charge carriers recombine on their way to the contacts. Therefore, an optimum thickness can be found.

Citation Download Citation

Orit Skorka, Dan Sirbu, and Dileepan Joseph "Optimization of photodetector thickness in vertically-integrated image sensors", Proc. SPIE 7249, Sensors, Cameras, and Systems for Industrial/Scientific Applications X, 72490O (27 January 2009); https://doi.org/10.1117/12.805999

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