Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

Eitan Shauly; Israel Rotstein; Ram Peltinov; Sergei Latinski; Ofer Adan; Shimon Levi; Ovadya Menadeva

doi:10.1117/12.814098

23 March 2009 Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

Eitan Shauly, Israel Rotstein, Ram Peltinov, Sergei Latinski, Ofer Adan, Shimon Levi, Ovadya Menadeva

Author Affiliations +

Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72720S (2009) https://doi.org/10.1117/12.814098
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmaxTM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.

Citation Download Citation

Eitan Shauly, Israel Rotstein, Ram Peltinov, Sergei Latinski, Ofer Adan, Shimon Levi, and Ovadya Menadeva "Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72720S (23 March 2009); https://doi.org/10.1117/12.814098

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